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EURODAC
1995
IEEE
128views VHDL» more  EURODAC 1995»
13 years 11 months ago
Closeness metrics for system-level functional partitioning
An important system design task is the partitioning of system functionality for implementation among multiple system components, including partitions among hardware and software c...
Frank Vahid, Daniel D. Gajski
DATE
2006
IEEE
110views Hardware» more  DATE 2006»
14 years 1 months ago
Configurable multiprocessor platform with RTOS for distributed execution of UML 2.0 designed applications
This paper presents the design and full prototype implementation of a configurable multiprocessor platform that supports distributed execution of applications described in UML 2.0...
Tero Arpinen, Petri Kukkala, Erno Salminen, Marko ...
DATE
2007
IEEE
184views Hardware» more  DATE 2007»
14 years 1 months ago
New safety critical radio altimeter for airbus and related design flow
The latest generation of the ERT560 Digital Radio Altimeter (DRA) developed for the Airbus A380 is the result of Thales’ 40 years experience. Over 40,000 radio-altimeters have b...
D. Hairion, S. Emeriau, E. Combot, Michel Sarlotte
DFT
2005
IEEE
110views VLSI» more  DFT 2005»
14 years 1 months ago
A design flow for protecting FPGA-based systems against single event upsets
SRAM-based Field Programmable Gate Arrays (FPGAs) are very susceptible to Single Event Upsets (SEUs) that may have dramatic effects on the circuits they implement. In this paper w...
Luca Sterpone, Massimo Violante
ITC
2002
IEEE
81views Hardware» more  ITC 2002»
14 years 14 days ago
Design Rewiring Using ATPG
—Logic optimization is the step of the very large scale integration (VLSI) design cycle where the designer performs modifications on a design to satisfy different constraints suc...
Andreas G. Veneris, Magdy S. Abadir, Mandana Amiri