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ISCA
2011
IEEE
313views Hardware» more  ISCA 2011»
12 years 11 months ago
FabScalar: composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template
A growing body of work has compiled a strong case for the single-ISA heterogeneous multi-core paradigm. A single-ISA heterogeneous multi-core provides multiple, differently-design...
Niket Kumar Choudhary, Salil V. Wadhavkar, Tanmay ...
IJOE
2008
122views more  IJOE 2008»
13 years 6 months ago
Mixed Reality Environment for Web-Based Laboratory Interactive Learning
: This paper presents a web-based laboratory for distance learners by incorporating simulation and hardware implementation into web-based e-learning systems. It presents a developm...
Kasim M. Al-Aubidy
DAC
2007
ACM
14 years 8 months ago
Automatic Verification of External Interrupt Behaviors for Microprocessor Design
Interrupt behaviors, especially the external ones, are difficult to verify in a microprocessor design project in that they involve both interacting hardware and software. This pap...
Fu-Ching Yang, Wen-Kai Huang, Ing-Jer Huang
ASAP
2007
IEEE
150views Hardware» more  ASAP 2007»
13 years 11 months ago
Customizing Reconfigurable On-Chip Crossbar Scheduler
We present a design of a customized crossbar scheduler for on-chip networks. The proposed scheduler arbitrates on-demand interconnects, where physical topologies are identical to ...
Jae Young Hur, Todor Stefanov, Stephan Wong, Stama...
CN
2002
91views more  CN 2002»
13 years 7 months ago
VERA: an extensible router architecture
We recognize two trends in router design: increasing pressure to extend the set of services provided by the router and increasing diversity in the hardware components used to cons...
Scott Karlin, Larry L. Peterson