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» Experiences in Hardware Trojan Design and Implementation
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IEEEPACT
2003
IEEE
14 years 26 days ago
Memory Hierarchy Design for a Multiprocessor Look-up Engine
We investigate the implementation of IP look-up for core routers using multiple microengines and a tailored memory hierarchy. The main architectural concerns are limiting the numb...
Jean-Loup Baer, Douglas Low, Patrick Crowley, Neal...
DELTA
2010
IEEE
14 years 21 days ago
Notations for Multiphase Pipelines
— FPGAs, (Field-Programmable Gate Arrays) are often used for embedded image processing applications. Parallelism, and in particular pipelining, is the most suitable architecture ...
Christopher T. Johnston, Donald G. Bailey, Paul J....
DAC
2004
ACM
14 years 8 months ago
Dynamic FPGA routing for just-in-time FPGA compilation
Just-in-time (JIT) compilation has previously been used in many applications to enable standard software binaries to execute on different underlying processor architectures. Howev...
Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan
SIGCPR
2003
ACM
183views Hardware» more  SIGCPR 2003»
14 years 25 days ago
ERP training strategies: conceptual training and the formation of accurate mental models
Enterprise Resource Planning (ERP) systems are large, complex integrated software applications that often take years to implement. This study examined a major determinant of succe...
Tony Coulson, Conrad Shayo, Lorne Olfman, C. E. Ta...
SBACPAD
2007
IEEE
121views Hardware» more  SBACPAD 2007»
14 years 1 months ago
DTA-C: A Decoupled multi-Threaded Architecture for CMP Systems
One way to exploit Thread Level Parallelism (TLP) is to use architectures that implement novel multithreaded execution models, like Scheduled DataFlow (SDF). This latter model pro...
Roberto Giorgi, Zdravko Popovic, Nikola Puzovic