348 search results - page 60 / 70 » Experiences in Hardware Trojan Design and Implementation |
ASPLOS
1987
ACM
13 years 11 months ago
1987
ACM
This paper describes the design and implementation of virtual memory management within the CMU Mach Operating System and the experiences gained by the Mach kernel group in porting...
ICCAD
2004
IEEE
14 years 4 months ago
2004
IEEE
Abstract— High-level synthesis (HLS) of memory-intensive applications has featured several innovations in terms of enhancements made to the basic memory organization and data lay...
MICRO
2005
IEEE
14 years 1 months ago
2005
IEEE
Conventional processors use a fully-associative store queue (SQ) to implement store-load forwarding. Associative search latency does not scale well to capacities and bandwidths re...
MICRO
2002
IEEE
14 years 13 days ago
2002
IEEE
Register integration (or just integration) is a register renaming discipline that implements instruction reuse via physical register sharing. Initially developed to perform squash...
EMSOFT
2006
Springer
13 years 11 months ago
2006
Springer
Upper bounds on worst-case execution times, which are commonly called WCET, are a prerequisite for validating the temporal correctness of tasks in a real-time system. Due to the e...