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TVLSI
2010
13 years 3 months ago
C-Pack: A High-Performance Microprocessor Cache Compression Algorithm
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
Xi Chen, Lei Yang, Robert P. Dick, Li Shang, Haris...
DAC
2000
ACM
14 years 9 months ago
Can recursive bisection alone produce routable placements?
This work focuses on congestion-driven placement of standard cells into rows in the fixed-die context. We summarize the stateof-the-art after two decades of research in recursive ...
Andrew E. Caldwell, Andrew B. Kahng, Igor L. Marko...
SOSP
2009
ACM
14 years 5 months ago
Modular data storage with Anvil
Databases have achieved orders-of-magnitude performance improvements by changing the layout of stored data – for instance, by arranging data in columns or compressing it before ...
Mike Mammarella, Shant Hovsepian, Eddie Kohler
DAC
2005
ACM
14 years 9 months ago
User-perceived latency driven voltage scaling for interactive applications
Power has become a critical concern for battery-driven computing systems, on which many applications that are run are interactive. System-level voltage scaling techniques, such as...
Le Yan, Lin Zhong, Niraj K. Jha
DATE
2009
IEEE
137views Hardware» more  DATE 2009»
14 years 3 months ago
A self-adaptive system architecture to address transistor aging
—As semiconductor manufacturing enters advanced nanometer design paradigm, aging and device wear-out related degradation is becoming a major concern. Negative Bias Temperature In...
Omer Khan, Sandip Kundu