— Packet buffers in router/switch interfaces constitute a central element of packet networks. The appropriate sizing of these buffers is an important and open research problem. M...
A global barrier synchronizes all processors in a parallel system. This paper investigates algorithms that allow disjoint subsets of processors to synchronize independently and in...
Anja Feldmann, Thomas R. Gross, David R. O'Hallaro...
This paper explores optimization techniques of the synchronization mechanisms for MPSoCs based on complex interconnect (Network-on-Chip), targeted at future powerefficient system...
Transfers of high-quality multimedia content pose new demands on capacity and services provided by the contemporary high-speed computer networks. Transfer of stereoscopic video is...
Clock skew optimization continues to be an important concern in circuit designs. To overcome the influence caused by PVT variations, the automatic skew synchronization scheme can ...