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ASPLOS
2010
ACM
14 years 3 months ago
Conservation cores: reducing the energy of mature computations
Growing transistor counts, limited power budgets, and the breakdown of voltage scaling are currently conspiring to create a utilization wall that limits the fraction of a chip tha...
Ganesh Venkatesh, Jack Sampson, Nathan Goulding, S...
CASES
2009
ACM
14 years 3 months ago
CheckerCore: enhancing an FPGA soft core to capture worst-case execution times
Embedded processors have become increasingly complex, resulting in variable execution behavior and reduced timing predictability. On such processors, safe timing specifications e...
Jin Ouyang, Raghuveer Raghavendra, Sibin Mohan, Ta...
RECONFIG
2008
IEEE
225views VLSI» more  RECONFIG 2008»
14 years 3 months ago
A Hardware Filesystem Implementation for High-Speed Secondary Storage
Platform FPGAs are capable of hosting entire Linuxbased systems including standard peripherals, integrated network interface cards and even disk controllers on a single chip. File...
Ashwin A. Mendon, Ron Sass
CASES
2006
ACM
14 years 2 months ago
Limitations of special-purpose instructions for similarity measurements in media SIMD extensions
Microprocessor vendors have provided special-purpose instructions such as psadbw and pdist to accelerate the sumof-absolute differences (SAD) similarity measurement. The usefulne...
Asadollah Shahbahrami, Ben H. H. Juurlink, Stamati...
RSP
2005
IEEE
164views Control Systems» more  RSP 2005»
14 years 2 months ago
High Level Synthesis for Data-Driven Applications
Abstract— John von Neumann proposed his famous architecture in a context where hardware was very expensive and bulky. His goal was to maximize functionality with minimal hardware...
Etienne Bergeron, Xavier Saint-Mleux, Marc Feeley,...