375 search results - page 13 / 75 » Explicit gate delay model for timing evaluation |
ICCAD
2002
IEEE
14 years 4 months ago
2002
IEEE
Existing static timing analyzers make several assumptions about circuits, implicitly trading off accuracy for speed. In this paper we examine the validity of these assumptions, no...
ICCAD
2003
IEEE
14 years 28 days ago
2003
IEEE
Process variations have become a critical issue in performance verification of high-performance designs. We present a new, statistical timing analysis method that accounts for int...
TCAD
2008
13 years 7 months ago
2008
We present an efficient optimization scheme for gate sizing in the presence of process variations. Our method is a worst-case design scheme, but it reduces the pessimism involved i...
ORL
2008
13 years 7 months ago
2008
We consider polling systems with general service times and switch-over times, gated service at all queues and with general renewal arrival processes. We derive closed-form express...
FDL
2007
IEEE
14 years 2 months ago
2007
IEEE
The forthcoming OMG UML Profile for Modeling and Analysis of Real-Time Embedded systems (MARTE) aims, amongst other things, at providing a referential Time Model subprofile wher...