375 search results - page 14 / 75 » Explicit gate delay model for timing evaluation |
DAC
2008
ACM
14 years 8 months ago
2008
ACM
Many recent techniques for timing analysis under variability, in which delay is an explicit function of underlying parameters, may be described as parameterized timing analysis. T...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
We present an efficient optimization scheme for gate sizing in the presence of process variations. Using a posynomial delay model, the delay constraints are modified to incorporat...
ITC
1996
IEEE
13 years 11 months ago
1996
IEEE
A 25k gate Test Chip was designed and manufactured to evaluate different test methods for scan-designed circuits. The design of the chip, the experiment, and preliminary experimen...
DATE
2003
IEEE
14 years 28 days ago
2003
IEEE
Abstract — This paper defines a new diagnosis problem for diagnosing delay defects based upon statistical timing models. We illustrate the differences between the delay defect d...
DATE
2003
IEEE
14 years 28 days ago
2003
IEEE
In today’s deep-submicron designs, the interconnect delays contribute an increasing part to the overall performance of an implementation. Particularly when targeting field prog...