375 search results - page 15 / 75 » Explicit gate delay model for timing evaluation |
DAC
2004
ACM
14 years 8 months ago
2004
ACM
Current Static Timing Analysis (STA) techniques allow one to verify the timing of a circuit at different process corners which only consider cases where all the supplies are low o...
ICNP
2000
IEEE
14 years 1 days ago
2000
IEEE
In this paper, we consider a proportional delay model for Internet differentiated services. Under this model, an ISP can control the “spacing” of waiting times between differe...
VTS
2003
IEEE
14 years 28 days ago
2003
IEEE
— In this paper, we study the problem of delay defect diagnosis based on statistical timing models. We propose a diagnosis algorithm that can effectively utilize statistical timi...
PATMOS
2007
Springer
14 years 1 months ago
2007
Springer
—Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the...
ITC
2003
IEEE
14 years 28 days ago
2003
IEEE
A technique to derive test vectors that exercise the worstcase delay effects in a domino circuit in the presence of crosstalk is described. A model for characterizing the delay of...