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» Explicit gate delay model for timing evaluation
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DAC
2008
ACM
14 years 8 months ago
Driver waveform computation for timing analysis with multiple voltage threshold driver models
This paper introduces an accurate and efficient electrical analysis of logic gates modeled as Multiple Voltage Threshold Models (MVTM) loaded by the associated interconnect. MVTMs...
Peter Feldmann, Soroush Abbaspour, Debjit Sinha, G...
ICNS
2008
IEEE
14 years 2 months ago
Effairness: Dealing with Time in Congestion Control Evaluation
Congestion control algorithms are traditionally evaluated in contrast to ideal capacity allocations that specify instantaneous efficient fair rates for application sessions but i...
Sergey Gorinsky, Harrick M. Vin
PE
2010
Springer
116views Optimization» more  PE 2010»
13 years 6 months ago
A polling model with multiple priority levels
In this paper we consider a single-server cyclic polling system. Between visits to successive queues, the server is delayed by a random switch-over time. The order in which custom...
Marko A. A. Boon, Ivo J. B. F. Adan, Onno J. Boxma
VLDB
2008
ACM
127views Database» more  VLDB 2008»
14 years 7 months ago
Delay aware querying with Seaweed
Large highly distributed data sets are poorly supported by current query technologies. Applications such as endsystembased network management are characterized by data stored on l...
Dushyanth Narayanan, Austin Donnelly, Richard Mort...
ICCAD
1997
IEEE
122views Hardware» more  ICCAD 1997»
13 years 12 months ago
Approximate timing analysis of combinational circuits under the XBD0 model
This paper is concerned with approximate delay computation algorithms for combinational circuits. As a result of intensive research in the early 90’s [3, 8] efficient tools exi...
Yuji Kukimoto, Wilsin Gosti, Alexander Saldanha, R...