375 search results - page 32 / 75 » Explicit gate delay model for timing evaluation |
ISCC
2007
IEEE
14 years 2 months ago
2007
IEEE
Abstract— Interactive and other delay-sensitive applications are interested in keeping end-to-end delays of their packets minimal. Unfortunately, congestion control offered by Tr...
ISPD
1999
ACM
14 years 1 days ago
1999
ACM
In this paper, we consider delay optimization in multilayer detailed routing. Given a detailed routing by some detailed router, we iteratively improve the delays of critical nets ...
IMC
2007
ACM
13 years 9 months ago
2007
ACM
Packet delay and loss are two fundamental measures of performance. Using active probing to measure delay and loss typically involves sending Poisson probes, on the basis of the PA...
ISCAS
2003
IEEE
14 years 1 months ago
2003
IEEE
We propose an algorithm based on singular value decomposition (SVD) to reduce the number of process variation variables. With few process variation variables, fault simulation and...
GLVLSI
2005
IEEE
14 years 1 months ago
2005
IEEE
As timing requirements in today’s advanced VLSI designs become more aggressive, the need for automated tools to diagnose timing failures increases. This work presents two such a...