375 search results - page 35 / 75 » Explicit gate delay model for timing evaluation |
141
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SDL
2003
15 years 4 months ago
2003
Network on Chip (NoC) is a new paradigm for designing large and complex systems on chips (SoCs). In this paradigm, a packet switched network is provided for on-chip communication. ...
140
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FPGA
1999
ACM
15 years 7 months ago
1999
ACM
In this paper, we investigate the speed and area-efficiency of FPGAs employing “logic clusters” containing multiple LUTs and registers as their logic block. We introduce a ne...
130
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LPAR
1999
Springer
15 years 7 months ago
1999
Springer
In this work, we develop a partial evaluation technique for residuating functional logic programs, which generalize the concurrent computation models for logic programs with delays...
146
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ECRTS
2010
IEEE
15 years 4 months ago
2010
IEEE
It is challenging to support the timeliness of realtime data service requests in data-intensive real-time applications such as online auction or stock trading, while maintaining t...
130
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ASPDAC
2009
ACM
15 years 10 months ago
2009
ACM
— Recent advances in statistical timing analysis (SSTA) achieve great success in computing arrival times under variations by extending sum and maximum operations to random variab...