375 search results - page 3 / 75 » Explicit gate delay model for timing evaluation |
DFT
2002
IEEE
14 years 17 days ago
2002
IEEE
We propose an algorithm for gate-delay fault diagnosis. It is based on the inject-and-evaluate paradigm [1], in which the fault site(s) are predicted through a series of injection...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
Recent study shows that the existing first order canonical timing model is not sufficient to represent the dependency of the gate delay on the variation sources when processing an...
ICCAD
2000
IEEE
14 years 1 days ago
2000
IEEE
A high accuracy system for transistor-level static timing analysis is presented. Accurate static timing verification requires that individual gate and interconnect delays be accu...
DAC
2004
ACM
13 years 11 months ago
2004
ACM
There is an increased dominance of intra-die process variations, creating a need for an accurate and fast statistical timing analysis. Most of the recent proposed approaches assum...
DAC
2005
ACM
13 years 9 months ago
2005
ACM
We present an efficient and accurate gate sizing tool that employs a novel piecewise convex delay model, handling both rise and fall delays, for static CMOS gates. The delay model...