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» Exploiting Architecture in Experimental System Development
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MICRO
2010
IEEE
215views Hardware» more  MICRO 2010»
13 years 7 months ago
A Task-Centric Memory Model for Scalable Accelerator Architectures
This paper presents a task-centric memory model for 1000-core compute accelerators. Visual computing applications are emerging as an important class of workloads that can exploit ...
John H. Kelm, Daniel R. Johnson, Steven S. Lumetta...
ANSOFT
1998
140views more  ANSOFT 1998»
13 years 8 months ago
FORM: A Feature-Oriented Reuse Method with Domain-Specific Reference Architectures
Systematic discovery and exploitation of commonality across related software systems is a fundamental technical requirement for achieving successful software reuse. By examining a...
Kyo Chul Kang, Sajoong Kim, Jaejoon Lee, Kijoo Kim...
FPGA
2003
ACM
123views FPGA» more  FPGA 2003»
14 years 1 months ago
Wire type assignment for FPGA routing
The routing channels of an FPGA consist of wire segments of various types providing the tradeoff between performance and routability. In the routing architectures of recently dev...
Seokjin Lee, Hua Xiang, D. F. Wong, Richard Y. Sun
FPL
2005
Springer
107views Hardware» more  FPL 2005»
14 years 2 months ago
Programmable Numerical Function Generators: Architectures and Synthesis Method
This paper presents an architecture and a synthesis method for programmable numerical function generators of trigonometric functions, logarithm functions, square root, reciprocal,...
Tsutomu Sasao, Shinobu Nagayama, Jon T. Butler
ISCAS
2005
IEEE
125views Hardware» more  ISCAS 2005»
14 years 2 months ago
A methodology for partitioning DSP applications in hybrid reconfigurable systems
—In this paper, we describe an automated and formalized methodology for partitioning computational intensive applications between reconfigurable hardware blocks of different gran...
Michalis D. Galanis, Athanasios Milidonis, George ...