This paper presents a task-centric memory model for 1000-core compute accelerators. Visual computing applications are emerging as an important class of workloads that can exploit ...
John H. Kelm, Daniel R. Johnson, Steven S. Lumetta...
Systematic discovery and exploitation of commonality across related software systems is a fundamental technical requirement for achieving successful software reuse. By examining a...
Kyo Chul Kang, Sajoong Kim, Jaejoon Lee, Kijoo Kim...
The routing channels of an FPGA consist of wire segments of various types providing the tradeoff between performance and routability. In the routing architectures of recently dev...
Seokjin Lee, Hua Xiang, D. F. Wong, Richard Y. Sun
This paper presents an architecture and a synthesis method for programmable numerical function generators of trigonometric functions, logarithm functions, square root, reciprocal,...
—In this paper, we describe an automated and formalized methodology for partitioning computational intensive applications between reconfigurable hardware blocks of different gran...
Michalis D. Galanis, Athanasios Milidonis, George ...