Sciweavers

87 search results - page 10 / 18
» Exploiting Instruction Redundancy for Transient Fault Tolera...
Sort
View
CHES
2004
Springer
170views Cryptology» more  CHES 2004»
14 years 27 days ago
Concurrent Error Detection Schemes for Involution Ciphers
Because of the rapidly shrinking dimensions in VLSI, transient and permanent faults arise and will continue to occur in the near future in increasing numbers. Since cryptographic c...
Nikhil Joshi, Kaijie Wu, Ramesh Karri
HPCA
2006
IEEE
14 years 7 months ago
Reducing resource redundancy for concurrent error detection techniques in high performance microprocessors
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
Sumeet Kumar, Aneesh Aggarwal
TDSC
2010
111views more  TDSC 2010»
13 years 5 months ago
Using Underutilized CPU Resources to Enhance Its Reliability
—Soft errors (or Transient faults) are temporary faults that arise in a circuit due to a variety of internal noise and external sources such as cosmic particle hits. Though soft ...
Avi Timor, Avi Mendelson, Yitzhak Birk, Neeraj Sur...
BCS
2008
13 years 9 months ago
Hardware Dependability in the Presence of Soft Errors
Using formal verification for designing hardware designs free from logic design bugs has been an active area of research since the last 15 years. Technology has matured and we hav...
Ashish Darbari, Bashir M. Al-Hashimi
FPL
2006
Springer
103views Hardware» more  FPL 2006»
13 years 11 months ago
An Efficient Fault Tolerance Scheme for Preventing Single Event Disruptions in Reconfigurable Architectures
Reconfigurable architectures are becoming increasingly popular with space related design engineers as they are inherently flexible to meet multiple requirements and offer signific...
Sajid Baloch, Tughrul Arslan, Adrian Stoica