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» Exploiting Low Entropy to Reduce Wire Delay
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COMCOM
2004
114views more  COMCOM 2004»
13 years 7 months ago
WFI optimized PWGPS for wireless IP networks
The worst-case fairness index (WFI) has proved to be an important metric in the provision of fairness and bounded delay in both wired and wireless networks. A feature of wireless l...
Fei Xiang, Alan Marshall, Junzhou Luo
IEEEPACT
2002
IEEE
14 years 12 days ago
Efficient Interconnects for Clustered Microarchitectures
Clustering is an effective microarchitectural technique for reducing the impact of wire delays, the complexity, and the power requirements of microprocessors. In this work, we inv...
Joan-Manuel Parcerisa, Julio Sahuquillo, Antonio G...
HPCA
2005
IEEE
14 years 7 months ago
A Small, Fast and Low-Power Register File by Bit-Partitioning
A large multi-ported register file is indispensable for exploiting instruction level parallelism (ILP) in today's dynamically scheduled superscalar processors. The number of ...
Masaaki Kondo, Hiroshi Nakamura
ISM
2008
IEEE
111views Multimedia» more  ISM 2008»
14 years 1 months ago
Secure and Low Cost Selective Encryption for JPEG2000
Selective encryption is a new trend in content protection. It aims at reducing the amount of data to encrypt while achieving a sufficient and inexpensive security. This approach ...
Ayoub Massoudi, Frédéric Lefè...
DATE
2002
IEEE
154views Hardware» more  DATE 2002»
14 years 13 days ago
Low Power Error Resilient Encoding for On-Chip Data Buses
As technology scales toward deep submicron, on-chip interconnects are becoming more and more sensitive to noise sources such as power supply noise, crosstalk, radiation induced ef...
Davide Bertozzi, Luca Benini, Giovanni De Micheli