48 search results - page 6 / 10 » Exploiting Low Entropy to Reduce Wire Delay |
TC
2008
13 years 7 months ago
2008
On-chip interconnection networks (OCINs) have emerged as a modular and scalable solution for wire delay constraints in deep submicron VLSI design. OCIN research has shown that the ...
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
Chip multiprocessors (CMPs) are becoming a popular way of exploiting ever-increasing number of on-chip transistors. At the same time, the location of data on the chip can play a c...
VLSID
2005
IEEE
14 years 1 months ago
2005
IEEE
The primary advantage of using 3D-FPGA over 2D-FPGA is that the vertical stacking of active layers reduce the Manhattan distance between the components in 3D-FPGA than when placed...
PERCOM
2008
ACM
13 years 7 months ago
2008
ACM
Integrating p2p services in multi-hop ad hoc networks is today a hot topic. General multi-hop , and pervasive systems in particular, can greatly benefit from high-level middleware...
TCAD
1998
13 years 7 months ago
1998
Conventional scan design imposes considerable area and delay overhead by using larger scan
ip-
ops and additional scan wires without utilizing the functionality of the combinatio...