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IPPS
2010
IEEE
13 years 6 months ago
Exploiting inter-thread temporal locality for chip multithreading
Multi-core organizations increasingly support multiple threads per core. Threads on a core usually share a single first-level data cache, so thread schedulers must try to minimize ...
Jiayuan Meng, Jeremy W. Sheaffer, Kevin Skadron
ASMTA
2009
Springer
114views Mathematics» more  ASMTA 2009»
14 years 10 days ago
Improving the Efficiency of the Proxel Method by Using Individual Time Steps
Discrete stochastic models (DSM) are widely used in various application fields today. Proxel-based simulation can outperform discrete event-based approaches in the analysis of smal...
Claudia Krull, Robert Buchholz, Graham Horton
CASES
2004
ACM
14 years 1 months ago
Safely exploiting multithreaded processors to tolerate memory latency in real-time systems
A coarse-grain multithreaded processor can effectively hide long memory latencies by quickly switching to an alternate task when the active task issues a memory request, improving...
Ali El-Haj-Mahmoud, Eric Rotenberg
IPPS
2007
IEEE
14 years 2 months ago
Modeling of NAMD's Network Input/Output on Large PC Clusters
This study examined the interplay among processor speed, cluster interconnect and file I/O, using parallel applications to quantify interactions. We focused on a common case wher...
Nancy Tran, Daniel A. Reed
IEEEPACT
2000
IEEE
14 years 22 days ago
Exploring the Limits of Sub-Word Level Parallelism
Multimedia instruction set extensions have become a prominent feature in desktop microprocessor platforms, promising superior performance on a wide range of floating-point and int...
Kevin Scott, Jack W. Davidson