Sciweavers

83 search results - page 11 / 17
» Exploiting loop-dependent stream reuse for stream processors
Sort
View
DATE
2009
IEEE
138views Hardware» more  DATE 2009»
14 years 2 months ago
Cache aware compression for processor debug support
—During post-silicon processor debugging, we need to frequently capture and dump out the internal state of the processor. Since internal state constitutes all memory elements, th...
Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishna...
CGO
2006
IEEE
14 years 1 months ago
Constructing Virtual Architectures on a Tiled Processor
As the amount of available silicon resources on one chip increases, we have seen the advent of ever increasing parallel resources integrated on-chip. Many architectures use these ...
David Wentzlaff, Anant Agarwal
CTRSA
2005
Springer
138views Cryptology» more  CTRSA 2005»
14 years 1 months ago
CryptoGraphics: Secret Key Cryptography Using Graphics Cards
We study the feasibility of using Graphics Processing Units (GPUs) for cryptographic processing, by exploiting the ability for GPUs to simultaneously process large quantities of pi...
Debra L. Cook, John Ioannidis, Angelos D. Keromyti...
VLSID
2003
IEEE
183views VLSI» more  VLSID 2003»
14 years 8 months ago
Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks
We present an innovative design of an accurate, 2D DCT IDCT processor, which handles scaled and sub-sampled input blocks efficiently. In the IDCT mode, the latency of the processo...
Rohini Krishnan, Om Prakash Gangwal, Jos T. J. van...
ICS
2001
Tsinghua U.
14 years 3 days ago
Slice-processors: an implementation of operation-based prediction
We describe the Slice Processor micro-architecture that implements a generalized operation-based prefetching mechanism. Operation-based prefetchers predict the series of operation...
Andreas Moshovos, Dionisios N. Pnevmatikatos, Amir...