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ISCA
1997
IEEE
120views Hardware» more  ISCA 1997»
13 years 11 months ago
Run-Time Adaptive Cache Hierarchy Management via Reference Analysis
Improvements in main memory speeds have not kept pace with increasing processor clock frequency and improved exploitation of instruction-level parallelism. Consequently, the gap b...
Teresa L. Johnson, Wen-mei W. Hwu
RTAS
2005
IEEE
14 years 29 days ago
Bounding Worst-Case Data Cache Behavior by Analytically Deriving Cache Reference Patterns
While caches have become invaluable for higher-end architectures due to their ability to hide, in part, the gap between processor speed and memory access times, caches (and partic...
Harini Ramaprasad, Frank Mueller
ASPDAC
2006
ACM
109views Hardware» more  ASPDAC 2006»
14 years 1 months ago
Energy savings through embedded processing on disk system
Abstract— Many of today’s data-intensive applications manipulate disk-resident data sets. As a result, their overall behavior is tightly coupled with their disk performance. Un...
Seung Woo Son, Guangyu Chen, Mahmut T. Kandemir, F...
ICCD
2008
IEEE
192views Hardware» more  ICCD 2008»
14 years 4 months ago
Energy-aware opcode design
— Embedded processors are required to achieve high performance while running on batteries. Thus, they must exploit all the possible means available to reduce energy consumption w...
Balaji V. Iyer, Jason A. Poovey, Thomas M. Conte
CASES
2001
ACM
13 years 11 months ago
Combined partitioning and data padding for scheduling multiple loop nests
With the widening performance gap between processors and main memory, efficient memory accessing behavior is necessary for good program performance. Loop partition is an effective...
Zhong Wang, Edwin Hsing-Mean Sha, Xiaobo Hu