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SBCCI
2003
ACM
135views VLSI» more  SBCCI 2003»
14 years 3 months ago
Modeling a Reconfigurable System for Computing the FFT in Place via Rewriting-Logic
The growing adoption of reconfigurable architectures opens new implementation alternatives and creates new design challenges. In the case of dynamically reconfigurable architectur...
Mauricio Ayala-Rincón, Rodrigo B. Nogueira,...
IOPADS
1996
100views more  IOPADS 1996»
13 years 11 months ago
ENWRICH a Compute-Processor Write Caching Scheme for Parallel File Systems
Many parallel scientific applications need high-performance I/O. Unfortunately, end-to-end parallel-I/O performance has not been able to keep up with substantial improvements in p...
Apratim Purakayastha, Carla Schlatter Ellis, David...
TVCG
2012
184views Hardware» more  TVCG 2012»
12 years 6 days ago
Output-Sensitive Construction of Reeb Graphs
—The Reeb graph of a scalar function represents the evolution of the topology of its level sets. This paper describes a near-optimal output-sensitive algorithm for computing the ...
Harish Doraiswamy, Vijay Natarajan
ASPLOS
2010
ACM
14 years 1 months ago
Micro-pages: increasing DRAM efficiency with locality-aware data placement
Power consumption and DRAM latencies are serious concerns in modern chip-multiprocessor (CMP or multi-core) based compute systems. The management of the DRAM row buffer can signif...
Kshitij Sudan, Niladrish Chatterjee, David Nellans...
ICPP
2009
IEEE
14 years 4 months ago
Exploiting Simulation Slack to Improve Parallel Simulation Speed
Parallel simulation is a technique to accelerate microarchitecture simulation of CMPs by exploiting the inherent parallelism of CMPs. In this paper, we explore the simulation para...
Jianwei Chen, Murali Annavaram, Michel Dubois