59 search results - page 4 / 12 » Exploring Memory Hierarchy with ArchC |
ASPDAC
2004
ACM
14 years 27 days ago
2004
ACM
— For multimedia applications, loop buffering is an efficient mechanism to reduce the power in the instruction memory of embedded processors. In particular, software controlled ...
DAC
2009
ACM
14 years 2 months ago
2009
ACM
In this paper, we propose PDRAM, a novel energy efficient main memory architecture based on phase change random access memory (PRAM) and DRAM. The paper explores the challenges i...
ICS
1992
Tsinghua U.
13 years 11 months ago
1992
Tsinghua U.
Previous research has used program transformation to introduce parallelism and to exploit data locality. Unfortunately,these twoobjectives have usuallybeen considered independentl...
CODES
2001
IEEE
13 years 11 months ago
2001
IEEE
Comprehensive exploration of the design space parameters at the system-level is a crucial task to evaluate architectural tradeoffs accounting for both energy and performance const...
DATE
2010
IEEE
14 years 16 days ago
2010
IEEE
Abstract— Flash memory is widely used in consumer electronics products, such as cell-phones and music players, and is increasingly displacing hard disk drives as the primary stor...