59 search results - page 5 / 12 » Exploring Memory Hierarchy with ArchC |
DATE
1999
IEEE
13 years 11 months ago
1999
IEEE
We describe EXPRESSION, a language supporting architectural design space exploration for embedded Systems-onChip (SOC) and automatic generation of a retargetable compiler/simulato...
TPDS
2008
13 years 7 months ago
2008
Multicore architectures have been ruling the recent microprocessor design trend. This is due to different reasons: better performance, thread-level parallelism bounds in modern app...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
In recent years, increasing manufacturing density has allowed the development of Multi-Processor Systems-on-Chip (MPSoCs). Application-Specific Instruction Set Processors (ASIPs)...
SAC
2004
ACM
14 years 26 days ago
2004
ACM
Clustered L0 buffers are an interesting alternative to reduce energy consumption in the instruction memory hierarchy of embedded VLIW processors. Currently, the synthesis of L0 cl...
RSP
2003
IEEE
14 years 22 days ago
2003
IEEE
We describe cache architecture, intended for prototype-oriented IC platforms, that automatically finds the best cache configuration for a particular application. The cache itself ...