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IPPS
2007
IEEE
14 years 2 months ago
Packet Reordering in Network Processors
Network processors today consists of multiple parallel processors (microengines) with support for multiple threads to exploit packet level parallelism inherent in network workload...
S. Govind, R. Govindarajan, Joy Kuri
IROS
2006
IEEE
528views Robotics» more  IROS 2006»
14 years 1 months ago
Dynamic Path Planning for a 7-DOF Robot Arm
— We present an on-line, robust, and efficient path planner for the redundant Mitsubishi PA-10 arm with 7 degrees of freedom (DOF) in non-stationary environments. Because of the...
Stefan Klanke, Dmitry V. Lebedev, Robert Haschke, ...
IV
2003
IEEE
183views Visualization» more  IV 2003»
14 years 1 months ago
Visualisation of RDF(S)-based Information
As Resource Description Framework (RDF) reaches maturity, there is an increasing need for tools that support it. A common and natural representation for RDF data is a directed lab...
Alexandru Telea, Flavius Frasincar, Geert-Jan Houb...
ASPLOS
2006
ACM
13 years 11 months ago
Accurate and efficient regression modeling for microarchitectural performance and power prediction
We propose regression modeling as an efficient approach for accurately predicting performance and power for various applications executing on any microprocessor configuration in a...
Benjamin C. Lee, David M. Brooks
ASPDAC
1995
ACM
104views Hardware» more  ASPDAC 1995»
13 years 11 months ago
Power analysis of a 32-bit embedded microcontroller
A new approach for power analysis of microprocessorshas recently been proposed [1]. The idea is to look at the power consumption in a microprocessor from the point of view of the ...
Vivek Tiwari, Mike Tien-Chien Lee