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» Exploring the multiple-GPU design space
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ISLPED
2003
ACM
83views Hardware» more  ISLPED 2003»
14 years 3 months ago
Leakage power modeling and optimization in interconnection networks
Power will be the key limiter to system scalability as interconnection networks take up an increasingly significant portion of system power. In this paper, we propose an architec...
Xuning Chen, Li-Shiuan Peh
CASES
2006
ACM
14 years 1 months ago
Efficient architectures through application clustering and architectural heterogeneity
Customizing architectures for particular applications is a promising approach to yield highly energy-efficient designs for embedded systems. This work explores the benefits of arc...
Lukasz Strozek, David Brooks
GRAPHICSINTERFACE
2000
13 years 11 months ago
Are We All In the Same "Bloat"?
"Bloat", a term that has existed in the technical community for many years, has recently received attention in the popular press. The term has a negative connotation imp...
Joanna McGrenere, Gale Moore
ISCA
2008
IEEE
188views Hardware» more  ISCA 2008»
14 years 4 months ago
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
Dongkook Park, Soumya Eachempati, Reetuparna Das, ...
CASES
2006
ACM
14 years 4 months ago
Modeling heterogeneous SoCs with SystemC: a digital/MEMS case study
Designers of SoCs with non-digital components, such as analog or MEMS devices, can currently use high-level system design languages, such as SystemC, to model only the digital par...
Ankush Varma, Muhammad Yaqub Afridi, Akin Akturk, ...