621 search results - page 47 / 125 » Extending Platform-Based Design to Network on Chip Systems |
129
click to vote
ASAP
2006
IEEE
15 years 5 months ago
2006
IEEE
Several semi-parallel decoding architectures have been explored by researchers for the quasi-cyclic low density parity check (LDPC) codes. In these architectures, the reconfigurab...
136
click to vote
GLVLSI
2003
IEEE
15 years 9 months ago
2003
IEEE
We present a unique FPGA that uses a mix of digital and large-signal analog computation for the simulation of gene regulatory networks. The prototype IC consists of a 4x5 array of...
114
Voted
DSN
2008
IEEE
15 years 10 months ago
2008
IEEE
Many classes of applications are inherently tolerant to errors. One such class are applications designed for a human end user, where the capabilities of the human cognitive system...
181
Voted
HPDC
2012
IEEE
13 years 6 months ago
2012
IEEE
networking with a layer 2 abstraction provides a powerful model for virtualized wide-area distributed computing resources, including for high performance computing (HPC) on collec...
142
click to vote
LPNMR
2009
Springer
2009
Springer
Application of ASP for Automatic Synthesis of Flexible Multiprocessor Systems from Parallel Programs
15 years 10 months ago
Configurable on chip multiprocessor systems combine advantages of task-level parallelism and the flexibility of field-programmable devices to customize architectures for paralle...