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    VLSID
    2007
    IEEE
    104views VLSI» more  VLSID 2007»
    Customization of Register File Banking Architecture for Low Power
    14 years 8 months ago
    Customization of Register File Banking Architecture for Low Power
    Download  www.cse.iitd.ernet.in
    Register file banking is an effective alternative to monolithic register files in embedded processor based systems. In this work, we propose techniques for performing application s...
    Rakesh Nalluri, Rohan Garg, Preeti Ranjan Panda
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    VLSISP
    2008
    203views more  VLSISP 2008»
    FPGA-based System for Real-Time Video Texture Analysis
    13 years 7 months ago
    FPGA-based System for Real-Time Video Texture Analysis
    Download  rtsimage.di.uoa.gr
    This paper describes a novel system for real-time video texture analysis. The system utilizes hardware to extract 2nd -order statistical features from video frames. These features ...
    Dimitrios E. Maroulis, Dimitrios K. Iakovidis, Dim...
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    CODES
    2009
    IEEE
    90views Software Engineering» more  CODES 2009»
    A variation-tolerant scheduler for better than worst-case behavioral synthesis
    14 years 2 months ago
    A variation-tolerant scheduler for better than worst-case behavioral synthesis
    Download  cadlab.cs.ucla.edu
    – There has been a recent shift in design paradigms, with many turning towards yield-driven approaches to synthesize and design systems. A major cause of this shift is the contin...
    Jason Cong, Albert Liu, Bin Liu
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    VLSID
    2003
    IEEE
    180views VLSI» more  VLSID 2003»
    Automating Formal Modular Verification of Asynchronous Real-Time Embedded Systems
    14 years 8 months ago
    Automating Formal Modular Verification of Asynchronous Real-Time Embedded Systems
    Download  www.cs.ccu.edu.tw
    Most verification tools and methodologies such as model checking, equivalence checking, hardware verification, software verification, and hardware-software coverification often fl...
    Pao-Ann Hsiung, Shu-Yu Cheng
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    DATE
    2008
    IEEE
    145views Hardware» more  DATE 2008»
    Minimizing Virtual Channel Buffer for Routers in On-chip Communication Architectures
    14 years 2 months ago
    Minimizing Virtual Channel Buffer for Routers in On-chip Communication Architectures
    Download  www.date-conference.com
    We present a novel methodology for design space exploration using a two-steps scheme to optimize the number of virtual channel buffers (buffers take the premier share of the route...
    Mohammad Abdullah Al Faruque, Jörg Henkel
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