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» Extremely Low-Power Logic
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ICFP
2012
ACM
11 years 10 months ago
Transporting functions across ornaments
Programming with dependent types is a blessing and a curse. It is a blessing to be able to bake invariants into the definition of datatypes: we can finally write correct-by-cons...
Pierre-Évariste Dagand, Conor McBride
ISLPED
2004
ACM
169views Hardware» more  ISLPED 2004»
14 years 1 months ago
Delay optimal low-power circuit clustering for FPGAs with dual supply voltages
This paper presents a delay optimal FPGA clustering algorithm targeting low power. We assume that the configurable logic blocks of the FPGA can be programmed using either a high s...
Deming Chen, Jason Cong
ISLPED
2003
ACM
86views Hardware» more  ISLPED 2003»
14 years 26 days ago
Exploiting compiler-generated schedules for energy savings in high-performance processors
This paper develops a technique that uniquely combines the advantages of static scheduling and dynamic scheduling to reduce the energy consumed in modern superscalar processors wi...
Madhavi Gopal Valluri, Lizy Kurian John, Heather H...
ICCAD
2007
IEEE
153views Hardware» more  ICCAD 2007»
14 years 4 months ago
Checking equivalence of quantum circuits and states
Among the post-CMOS technologies currently under investigation, quantum computing (QC) holds a special place. QC offers not only extremely small size and low power, but also expon...
George F. Viamontes, Igor L. Markov, John P. Hayes
ICCAD
2001
IEEE
127views Hardware» more  ICCAD 2001»
14 years 4 months ago
What is the Limit of Energy Saving by Dynamic Voltage Scaling?
Dynamic voltage scaling (DVS) is a technique that varies the supply voltage and clock frequency based on the computation load to provide desired performance with the minimal amoun...
Gang Qu