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ARITH
2007
IEEE
14 years 4 months ago
Decimal Floating-Point Adder and Multifunction Unit with Injection-Based Rounding
Shrinking feature sizes gives more headroom for designers to extend the functionality of microprocessors. The IEEE 754R working group has revised the IEEE 754-1985 Standard for Bi...
Liang-Kai Wang, Michael J. Schulte
CODES
2007
IEEE
14 years 4 months ago
Performance improvement of block based NAND flash translation layer
With growing capacities of flash memories, an efficient layer to manage read and write access to flash is required. NFTL is a widely used block based flash translation layer de...
Siddharth Choudhuri, Tony Givargis
ICMCS
2007
IEEE
107views Multimedia» more  ICMCS 2007»
14 years 4 months ago
Power Efficient Motion Estimation using Multiple Imprecise Metric Computations
In this paper, we propose power efficient motion estimation (ME) using multiple imprecise sum absolute difference (SAD) metric computations. We extend recent work in [18] by prov...
In Suk Chong, Antonio Ortega
ISCA
2007
IEEE
143views Hardware» more  ISCA 2007»
14 years 4 months ago
Interconnect design considerations for large NUCA caches
The ever increasing sizes of on-chip caches and the growing domination of wire delay necessitate significant changes to cache hierarchy design methodologies. Many recent proposal...
Naveen Muralimanohar, Rajeev Balasubramonian
RTSS
2007
IEEE
14 years 4 months ago
Distributed Minimal Time Convergecast Scheduling for Small or Sparse Data Sources
— Many applications of sensor networks require the base station to collect all the data generated by sensor nodes. As a consequence many-to-one communication pattern, referred to...
Ying Zhang, Shashidhar Gandham, Qingfeng Huang