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TC
2010
13 years 3 months ago
FPGA Designs with Optimized Logarithmic Arithmetic
Using a general polynomial approximation approach, we present an arithmetic library generator for the logarithmic number system (LNS). The generator produces optimized LNS arithmet...
Haohuan Fu, Oskar Mencer, Wayne Luk
DSD
2010
IEEE
140views Hardware» more  DSD 2010»
13 years 9 months ago
RobuCheck: A Robustness Checker for Digital Circuits
Abstract—Continuously shrinking feature sizes cause an increasing vulnerability of digital circuits. Manufacturing failures and transient faults may tamper the functionality. Aut...
Stefan Frehse, Görschwin Fey, André S&...
VLSID
2002
IEEE
119views VLSI» more  VLSID 2002»
14 years 9 months ago
Reducing Library Development Cycle Time through an Optimum Layout Create Flow
One of the major roadblocks in reduction of library generation cycle time is the layout generation phase. The two methods of doing automatic layout generation are synthesis and mig...
Rituparna Mandal, Dibyendu Goswami, Arup Dash
COMPSAC
2002
IEEE
14 years 1 months ago
From MSC and UML to SDL
UML and MSC are widely used by software practitioners. SDL is an ITU standard language for telecommunications software specification. It has a formal semantics, and is supported b...
Stephan Bourduas, Ferhat Khendek, Daniel Vincent
IPPS
2007
IEEE
14 years 3 months ago
Biomolecular Path Sampling Enabled by Processing in Network Storage
Computationally complex and data intensive atomic scale biomolecular simulation is enabled via Processing in Network Storage (PINS): a novel distributed system framework to overco...
Paul Brenner, Justin M. Wozniak, Douglas Thain, Aa...