Sciweavers

19 search results - page 2 / 4
» FELIX: Using Rewriting-Logic for Generating Functionally Equ...
Sort
View
DAC
2006
ACM
14 years 11 months ago
Transistor abstraction for the functional verification of FPGAs
or Abstraction for the Functional Verification of FPGAs Guy Dupenloup, Thierry Lemeunier, Roland Mayr Altera Corporation 101 Innovation Drive San Jose, CA 95134 1-408-544-8672 {gdu...
Guy Dupenloup, Thierry Lemeunier, Roland Mayr
ICFP
2005
ACM
14 years 10 months ago
Scrap your nameplate: (functional pearl)
Recent research has shown how boilerplate code, or repetitive code for traversing datatypes, can be eliminated using generic programming techniques already available within some i...
James Cheney
JSA
2008
131views more  JSA 2008»
13 years 10 months ago
Formal verification of ASMs using MDGs
We present a framework for the formal verification of abstract state machine (ASM) designs using the multiway decision graphs (MDG) tool. ASM is a state based language for describ...
Amjad Gawanmeh, Sofiène Tahar, Kirsten Wint...
RSP
2003
IEEE
176views Control Systems» more  RSP 2003»
14 years 4 months ago
Rapid Design and Analysis of Communication Systems Using the BEE Hardware Emulation Environment
This paper describes the early analysis and estimation features currently implemented in the Berkeley Emulation Engine (BEE) system. BEE is an integrated rapid prototyping and des...
Chen Chang, Kimmo Kuusilinna, Brian C. Richards, A...
EUROSYS
2007
ACM
14 years 8 months ago
Melange: creating a "functional" internet
Most implementations of critical Internet protocols are written in type-unsafe languages such as C or C++ and are regularly vulnerable to serious security and reliability problems...
Anil Madhavapeddy, Alex Ho, Tim Deegan, David Scot...