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MICRO
2006
IEEE
135views Hardware» more  MICRO 2006»
14 years 3 months ago
Support for High-Frequency Streaming in CMPs
As the industry moves toward larger-scale chip multiprocessors, the need to parallelize applications grows. High inter-thread communication delays, exacerbated by over-stressed hi...
Ram Rangan, Neil Vachharajani, Adam Stoler, Guilhe...
LCTRTS
2010
Springer
14 years 1 months ago
Cache vulnerability equations for protecting data in embedded processor caches from soft errors
Continuous technology scaling has brought us to a point, where transistors have become extremely susceptible to cosmic radiation strikes, or soft errors. Inside the processor, cac...
Aviral Shrivastava, Jongeun Lee, Reiley Jeyapaul
TCAD
2008
127views more  TCAD 2008»
13 years 9 months ago
Speculative Loop-Pipelining in Binary Translation for Hardware Acceleration
Abstract--Multimedia and DSP applications have several computationally intensive kernels which are often offloaded and accelerated by application-specific hardware. This paper pres...
Sejong Oh, Tag Gon Kim, Jeonghun Cho, Elaheh Bozor...
ICMCS
2007
IEEE
123views Multimedia» more  ICMCS 2007»
14 years 3 months ago
Efficient Parallelization of H.264 Decoding with Macro Block Level Scheduling
The H.264 decoder has a sequential, control intensive front end that makes it difficult to leverage the potential performance of emerging manycore processors. Preparsing is a fun...
Jike Chong, Nadathur Satish, Bryan C. Catanzaro, K...
PPDP
2005
Springer
14 years 2 months ago
Self-tuning resource aware specialisation for prolog
The paper develops a self-tuning resource aware partial evaluation technique for Prolog programs, which derives its own control strategies tuned for the underlying computer archit...
Stephen-John Craig, Michael Leuschel