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CASES
2004
ACM
14 years 1 months ago
Balancing design options with Sherpa
Application specific processors offer the potential of rapidly designed logic specifically constructed to meet the performance and area demands of the task at hand. Recently, t...
Timothy Sherwood, Mark Oskin, Brad Calder
ISLPED
2004
ACM
139views Hardware» more  ISLPED 2004»
14 years 29 days ago
Eliminating voltage emergencies via microarchitectural voltage control feedback and dynamic optimization
Microprocessor designers use techniques such as clock gating to reduce power dissipation. An unfortunate side-effect of these techniques is the processor current fluctuations th...
Kim M. Hazelwood, David Brooks
CASES
2003
ACM
14 years 24 days ago
Extending STI for demanding hard-real-time systems
Software thread integration (STI) is a compilation technique which enables the efficient use of an application’s fine-grain idle time on generic processors without special hardw...
Benjamin J. Welch, Shobhit O. Kanaujia, Adarsh See...
IWMM
2010
Springer
118views Hardware» more  IWMM 2010»
14 years 10 days ago
Speculative parallelization using state separation and multiple value prediction
With the availability of chip multiprocessor (CMP) and simultaneous multithreading (SMT) machines, extracting thread level parallelism from a sequential program has become crucial...
Chen Tian, Min Feng, Rajiv Gupta
MICRO
1998
IEEE
144views Hardware» more  MICRO 1998»
13 years 11 months ago
Analyzing the Working Set Characteristics of Branch Execution
To achieve highly accurate branch prediction, it is necessary not only to allocate more resources to branch prediction hardware but also to improve the understanding of branch exe...
Sangwook P. Kim, Gary S. Tyson