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FPL
2005
Springer
96views Hardware» more  FPL 2005»
14 years 2 months ago
Dynamic Reconfiguration with hardwired Networks-on-Chip on future FPGAs
Due to their layered approach, Networks-on-Chip (NoC) are a promising communication backbone in the field of heterogeneous dynamically reconfigurable systems. In this paper a fu...
Ronald Hecht, Stephan Kubisch, Andreas Herrholtz, ...
IANDC
2006
121views more  IANDC 2006»
13 years 8 months ago
Comparing operational models of name-passing process calculi
We study three operational models of name-passing process calculi: coalgebras on (pre)sheaves, indexed labelled transition systems, and history dependent automata. The coalgebraic...
Marcelo P. Fiore, Sam Staton
FPGA
2010
ACM
232views FPGA» more  FPGA 2010»
13 years 8 months ago
High-throughput bayesian computing machine with reconfigurable hardware
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
Mingjie Lin, Ilia Lebedev, John Wawrzynek
ISCA
1995
IEEE
93views Hardware» more  ISCA 1995»
14 years 4 days ago
Optimizing Memory System Performance for Communication in Parallel Computers
Communicationin aparallel systemfrequently involvesmoving data from the memory of one node to the memory of another; this is the standard communication model employedin message pa...
Thomas Stricker, Thomas R. Gross
ARITH
1999
IEEE
14 years 28 days ago
Montgomery Modular Exponentiation on Reconfigurable Hardware
It is widely recognized that security issues will play a crucial role in the majority of future computer and communication systems. Central tools for achieving system security are...
Thomas Blum