145 search results - page 4 / 29 » FPGA Design Automation: A Survey |
175
click to vote
ASPDAC
2012
ACM
14 years 1 months ago
2012
ACM
Behavioral synthesis tools have made significant progress in compiling high-level programs into register-transfer level (RTL) specifications. But manually rewriting code is still ...
177
click to vote
DAC
2004
ACM
16 years 6 months ago
2004
ACM
Just-in-time (JIT) compilation has previously been used in many applications to enable standard software binaries to execute on different underlying processor architectures. Howev...
DAC
2000
ACM
16 years 6 months ago
2000
ACM
161
click to vote
TCAD
2008
15 years 5 months ago
2008
The quality and the correctness of software is often the greatest concern in electronic systems. Formal verification tools can provide a guarantee that a design is free of specific...
158
click to vote
DAC
2006
ACM
16 years 6 months ago
2006
ACM
In this paper we propose a hybrid FPGA using nanoscale clusters with an architecture similar to clusters of traditional CMOS FPGAs. The proposed cluster is made of a crossbar of n...