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DAC
2005
ACM
14 years 8 months ago
Device and architecture co-optimization for FPGA power reduction
Device optimization considering supply voltage Vdd and threshold voltage Vt tuning does not increase chip area but has a great impact on power and performance in the nanometer tec...
Lerong Cheng, Phoebe Wong, Fei Li, Yan Lin, Lei He
HPCA
2007
IEEE
14 years 7 months ago
Implications of Device Timing Variability on Full Chip Timing
As process technologies continue to scale, the magnitude of within-die device parameter variations is expected to increase and may lead to significant timing variability. This pap...
Murali Annavaram, Ed Grochowski, Paul Reed
FPGA
2000
ACM
168views FPGA» more  FPGA 2000»
13 years 11 months ago
A benchmark suite for evaluating configurable computing systems--status, reflections, and future directions
This paper presents a benchmark suite for evaluating a configurable computing system's infrastructure, both tools and architecture. A novel aspect of this work is the use of ...
S. Kumar, Luiz Pires, Subburajan Ponnuswamy, C. Na...
ARC
2010
Springer
178views Hardware» more  ARC 2010»
14 years 1 months ago
An Analysis of Delay Based PUF Implementations on FPGA
Physical Unclonable Functions promise cheap, efficient, and secure identification and authentication of devices. In FPGA devices, PUFs may be instantiated directly from FPGA fabri...
Sergey Morozov, Abhranil Maiti, Patrick Schaumont
FPGA
2000
ACM
175views FPGA» more  FPGA 2000»
13 years 11 months ago
An FPGA implementation and performance evaluation of the Serpent block cipher
With the expiration of the Data Encryption Standard (DES) in 1998, the Advanced Encryption Standard (AES) development process is well underway. It is hoped that the result of the ...
Adam J. Elbirt, Christof Paar