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» FPGA interconnect design using logical effort
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FPGA
2007
ACM
185views FPGA» more  FPGA 2007»
14 years 1 months ago
Power-aware FPGA logic synthesis using binary decision diagrams
Power consumption in field programmable gate arrays (FPGAs) has become an important issue as the FPGA market has grown to include mobile platforms. In this work we present a power...
Kevin Oo Tinmaung, David Howland, Russell Tessier
FCCM
1998
IEEE
170views VLSI» more  FCCM 1998»
13 years 11 months ago
Characterization and Parameterization of a Pipeline Reconfigurable FPGA
ended abstract defines a class of architectures for pipeline reconfigurable FPGAs by parameterizing a generic model. This class of architectures is sufficiently general to allow e...
Matthew Moe, Herman Schmit, Seth Copen Goldstein
ERSA
2007
142views Hardware» more  ERSA 2007»
13 years 9 months ago
An FPGA Implementation of Reciprocal Sums for SPME
Molecular Dynamics simulations have become an interesting target for acceleration using Field-Programmable Gate Arrays (FPGA). Still to be attempted completely in FPGA hardware is...
Sam Lee, Paul Chow
GLVLSI
2007
IEEE
154views VLSI» more  GLVLSI 2007»
14 years 1 months ago
A design kit for a fully working shared memory multiprocessor on FPGA
This paper presents a framework to design a shared memory multiprocessor on a programmable platform. We propose a complete flow, composed by a programming model and a template ar...
Antonino Tumeo, Matteo Monchiero, Gianluca Palermo...
DAC
2002
ACM
14 years 8 months ago
IP delivery for FPGAs using Applets and JHDL
This paper introduces an FPGA IP evaluation and delivery system that operates within Java applets. The use of such applets allows designers to create, evaluate, test, and obtain F...
Michael J. Wirthlin, Brian McMurtrey