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» FPGA interconnect design using logical effort
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FPGA
2004
ACM
119views FPGA» more  FPGA 2004»
14 years 28 days ago
In-system FPGA prototyping of an itanium microarchitecture
We describe an effort to prototype an Itanium microarchitecture using an FPGA. The microarchitecture model is written in the Bluespec hardware description language (HDL) and suppo...
Roland E. Wunderlich, James C. Hoe
ISCAS
1999
IEEE
129views Hardware» more  ISCAS 1999»
13 years 11 months ago
Fuzzy logic damping controller for FACTS devices in interconnected power systems
In this paper fuzzy controllers are designed for FACTS devices in interconnected power systems. Two typical FACTS devices, STATCOM and UPFC, are used as examples to show that FACT...
Ni Yixin, Mak Lai On, Huang Zhenyu, Chen Shousun, ...
RECONFIG
2009
IEEE
172views VLSI» more  RECONFIG 2009»
14 years 2 months ago
Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow
Abstract—The main challenge when implementing cryptographic algorithms in hardware is to protect them against attacks that target directly the device. Two strategies are customar...
Shivam Bhasin, Jean-Luc Danger, Florent Flament, T...
ASAP
2002
IEEE
76views Hardware» more  ASAP 2002»
14 years 15 days ago
A Component Architecture for FPGA-Based, DSP System Design
† Introducing FPGA components into DSP system implementations creates an assortment of challenges across system architecture and logic design. Recognizing that some of the greate...
Gary Spivey, Shuvra S. Bhattacharyya, Kazuo Nakaji...
DAC
2004
ACM
14 years 8 months ago
Dynamic FPGA routing for just-in-time FPGA compilation
Just-in-time (JIT) compilation has previously been used in many applications to enable standard software binaries to execute on different underlying processor architectures. Howev...
Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan