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» FPGA interconnect design using logical effort
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DATE
2002
IEEE
206views Hardware» more  DATE 2002»
14 years 15 days ago
Accurate Area and Delay Estimators for FPGAs
We present an area and delay estimator in the context of a compiler that takes in high level signal and image processing applications described in MATLAB and performs automatic de...
Anshuman Nayak, Malay Haldar, Alok N. Choudhary, P...
FPGA
2006
ACM
113views FPGA» more  FPGA 2006»
13 years 11 months ago
Optimality study of logic synthesis for LUT-based FPGAs
Abstract--Field-programmable gate-array (FPGA) logic synthesis and technology mapping have been studied extensively over the past 15 years. However, progress within the last few ye...
Jason Cong, Kirill Minkovich
SAMOS
2007
Springer
14 years 1 months ago
FPGA Design Methodology for a Wavelet-Based Scalable Video Decoder
Client-side diversification led the video-coding community to develop scalable video-codecs supporting efficient decoding at varying quality levels. This scalability has a lot of...
Hendrik Eeckhaut, Harald Devos, Philippe Faes, Mar...
FPGA
2003
ACM
138views FPGA» more  FPGA 2003»
14 years 23 days ago
Automatic transistor and physical design of FPGA tiles from an architectural specification
One of the most difficult and time-consuming steps in the creation of an FPGA is its transistor-level design and physical layout. Modern commercial FPGAs typically consume anywher...
Ketan Padalia, Ryan Fung, Mark Bourgeault, Aaron E...
FPGA
1997
ACM
118views FPGA» more  FPGA 1997»
13 years 11 months ago
Module Generation of Complex Macros for Logic-Emulation Applications
Logic emulation is a technique that uses dynamically reprogrammable systems for prototyping and design veri cation. Using an emulator, designers can realize designs through a soft...
Wen-Jong Fang, Allen C.-H. Wu, Duan-Ping Chen