363 search results - page 24 / 73 » FPGA interconnect design using logical effort |
DAC
2004
ACM
13 years 11 months ago
2004
ACM
In System on Chip (SoC) design, growing design complexity has esigners to start designs at higher abstraction levels. This paper proposes an SoC design methodology that makes full...
ICES
2000
Springer
13 years 11 months ago
2000
Springer
Abstract. An evolutionary algorithm is used to evolve a digital circuit which computes a simple hash function mapping a 16-bit address space into an 8-bit one. The target technolog...
FPL
2008
Springer
13 years 9 months ago
2008
Springer
Abstract-The network on chip will become a future general purpose interconnect for FPGAs much like today's standard OPB or PLB bus architectures. However, performance characte...
FPL
2009
Springer
14 years 5 days ago
2009
Springer
In this paper we present a verification platform designed for HyperTransport 3.x (HT3) applications. HyperTransport 3.x is a very low latency and high bandwidth chip-tochip interc...
DAC
2001
ACM
14 years 8 months ago
2001
ACM
This work presents a new and computationally efficient performance optimization technique for distributed RLC interconnects based on a rigorous delay computation scheme. The new o...