363 search results - page 29 / 73 » FPGA interconnect design using logical effort |
114
Voted
FCCM
2009
IEEE
15 years 10 months ago
2009
IEEE
—Single-FPGA spatial implementations can provide an order of magnitude speedup over sequential microprocessor implementations for data-parallel, floating-point computation in SP...
115
Voted
FPL
2006
Springer
15 years 7 months ago
2006
Springer
This paper presents FPGA implementations of the DES and Triple-DES with improved security against power analysis attacks. The proposed designs use Boolean masking, a previously in...
133
Voted
FPGA
2009
ACM
15 years 10 months ago
2009
ACM
Many natural processes exhibit exponential decay and, consequently, computational scientists make extensive use of e−x in computer simulation experiments. While it is common to ...
101
Voted
ISCAS
2006
IEEE
15 years 9 months ago
2006
IEEE
Abstract— Networks-on-chip (NoCs) are a scalable interconnect solution to large scale multiprocessor systems on chip and are rapidly becoming reality. As the ratio of embedded co...
141
Voted
FPGA
2009
ACM
15 years 10 months ago
2009
ACM
Via-programmable gate arrays (VPGAs) offer a middle ground between application specific integrated circuits and field programmable gate arrays in terms of flexibility, manufac...