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» FPGA interconnect design using logical effort
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DAC
2008
ACM
14 years 8 months ago
TuneFPGA: post-silicon tuning of dual-Vdd FPGAs
Modern CMOS manufacturing processes have significant variability, which necessitates guard banding to achieve reasonable yield. We study an FPGA architecture with a dual voltage s...
Stephen Bijansky, Adnan Aziz
ARC
2010
Springer
177views Hardware» more  ARC 2010»
14 years 2 months ago
An FPGA-Based Real-Time Event Sampler
This paper presents the design and FPGA-implementation of a sampler that is suited for sampling real-time events in embedded systems. Such sampling is useful, for example, to test ...
Niels Penneman, Luc Perneel, Martin Timmerman, Bjo...
FPGA
2006
ACM
224views FPGA» more  FPGA 2006»
13 years 11 months ago
Flexible implementation of genetic algorithms on FPGAs
In this paper, we propose a technique to flexibly implement genetic algorithms for various problems on FPGAs. For the purpose, we propose a basic architecture for GA which consist...
Tatsuhiro Tachibana, Yoshihiro Murata, Naoki Shiba...
DAGSTUHL
2006
13 years 9 months ago
Pre-Routed FPGA Cores for Rapid System Construction in a Dynamic Reconfigurable System
This paper presents a method of constructing pre-routed FPGA cores which lays the foundations for a rapid system construction framework for dynamically reconfigurable computing sy...
Douglas L. Maskell, Timothy F. Oliver
FPGA
2004
ACM
234views FPGA» more  FPGA 2004»
13 years 11 months ago
An embedded true random number generator for FPGAs
Field Programmable Gate Arrays (FPGAs) are an increasingly popular choice of platform for the implementation of cryptographic systems. Until recently, designers using FPGAs had le...
Paul Kohlbrenner, Kris Gaj