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» FPGA interconnect design using logical effort
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DATE
2007
IEEE
85views Hardware» more  DATE 2007»
14 years 3 months ago
Timing simulation of interconnected AUTOSAR software-components
AUTOSAR is a recent specification initiative which focuses on a model-driven architecture like methodology for automotive applications. However, needed engineering steps, or how-t...
Matthias Krause, Oliver Bringmann, André He...
SBCCI
2004
ACM
111views VLSI» more  SBCCI 2004»
14 years 2 months ago
A partial reconfigurable architecture for controllers based on Petri nets
Digital Control System in the industry has been used in most of the applications based on expensive Programmable Logical Controllers (PLC). These Systems are, in general, highly c...
Paulo Sérgio B. do Nascimento, Paulo Romero...
INTEGRATION
2008
183views more  INTEGRATION 2008»
13 years 8 months ago
Network-on-Chip design and synthesis outlook
With the growing complexity in consumer embedded products, new tendencies forecast heterogeneous Multi-Processor SystemsOn-Chip (MPSoCs) consisting of complex integrated component...
David Atienza, Federico Angiolini, Srinivasan Mura...
DAC
2004
ACM
14 years 9 months ago
A method to decompose multiple-output logic functions
This paper shows a method to decompose a given multipleoutput circuit into two circuits with intermediate outputs. We use a BDD for characteristic function (BDD for CF) to represe...
Tsutomu Sasao, Munehiro Matsuura
FPGA
2006
ACM
111views FPGA» more  FPGA 2006»
14 years 13 days ago
FPGA clock network architecture: flexibility vs. area and power
This paper examines the tradeoffs between flexibility, area, and power dissipation of programmable clock networks for FieldProgrammable Gate Arrays (FPGA's). The paper begins...
Julien Lamoureux, Steven J. E. Wilton