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» FPGA interconnect design using logical effort
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POPL
2010
ACM
13 years 10 months ago
Reconfigurable asynchronous logic automata: (RALA)
Computer science has served to insulate programs and programmers from knowledge of the underlying mechanisms used to manipulate information, however this fiction is increasingly h...
Neil Gershenfeld, David Dalrymple, Kailiang Chen, ...
DAC
2006
ACM
14 years 8 months ago
NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture
Recent progress on nanodevices, such as carbon nanotubes and nanowires, points to promising directions for future circuit design. However, nanofabrication techniques are not yet m...
Wei Zhang, Niraj K. Jha, Li Shang
DAC
2006
ACM
14 years 8 months ago
SAT sweeping with local observability don't-cares
SAT sweeping is a method for simplifying an AND/INVERTER graph (AIG) by systematically merging graph vertices from the inputs towards the outputs using a combination of structural...
Qi Zhu, Nathan Kitchen, Andreas Kuehlmann, Alberto...
ICFP
2003
ACM
14 years 7 months ago
Representing reductions of NP-complete problems in logical frameworks: a case study
Under the widely believed conjecture P=NP, NP-complete problems cannot be solved exactly using efficient polynomial time algorithms. Furthermore, any instance of a NP-complete pro...
Carsten Schürmann, Jatin Shah
FPL
2010
Springer
180views Hardware» more  FPL 2010»
13 years 5 months ago
A Karatsuba-Based Montgomery Multiplier
Abstract--Modular multiplication of long integers is an important building block for cryptographic algorithms. Although several FPGA accelerators have been proposed for large modul...
Gary Chun Tak Chow, Ken Eguro, Wayne Luk, Philip L...