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» FPGA interconnect design using logical effort
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ICCAD
1997
IEEE
137views Hardware» more  ICCAD 1997»
13 years 11 months ago
Optimization techniques for high-performance digital circuits
The relentless push for high performance in custom digital circuits has led to renewed emphasis on circuit optimization or tuning. The parameters of the optimization are typically...
Chandramouli Visweswariah
ISQED
2011
IEEE
230views Hardware» more  ISQED 2011»
12 years 11 months ago
Constraint generation for software-based post-silicon bug masking with scalable resynthesis technique for constraint optimizatio
Due to the dramatic increase in design complexity, verifying the functional correctness of a circuit is becoming more difficult. Therefore, bugs may escape all verification effo...
Chia-Wei Chang, Hong-Zu Chou, Kai-Hui Chang, Jie-H...
CODES
2005
IEEE
14 years 1 months ago
Blue matter on blue gene/L: massively parallel computation for biomolecular simulation
This paper provides an overview of the Blue Matter application development effort within the Blue Gene project that supports our scientific simulation efforts in the areas of pro...
Robert S. Germain, Blake G. Fitch, Aleksandr Raysh...
TSC
2010
133views more  TSC 2010»
13 years 5 months ago
Semantic-Based Mashup of Composite Applications
—The need for integration of all types of client and server applications that were not initially designed to interoperate is gaining popularity. One of the reasons for this popul...
Anne H. H. Ngu, Michael Pierre Carlson, Quan Z. Sh...
ITC
1996
IEEE
107views Hardware» more  ITC 1996»
13 years 11 months ago
Orthogonal Scan: Low-Overhead Scan for Data Paths
Orthogonal scan paths, which follow the path of the data flow, can be used in data path designs to reduce the test overhead -- area, delay and test application time -- by sharing ...
Robert B. Norwood, Edward J. McCluskey