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» FPGA interconnect design using logical effort
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ICCD
2007
IEEE
206views Hardware» more  ICCD 2007»
14 years 4 months ago
SCAFFI: An intrachip FPGA asynchronous interface based on hard macros
Building fully synchronous VLSI circuits is becoming less viable as circuit geometries evolve. However, before the adoption of purely asynchronous strategies in VLSI design, globa...
Julian J. H. Pontes, Rafael Soares, Ewerson Carval...
TC
1998
13 years 7 months ago
Methodologies for Tolerating Cell and Interconnect Faults in FPGAs
—The very high levels of integration and submicron device sizes used in current and emerging VLSI technologies for FPGAs lead to higher occurrences of defects and operational fau...
Fran Hanchek, Shantanu Dutt
ASPDAC
2005
ACM
138views Hardware» more  ASPDAC 2005»
14 years 1 months ago
Crowdedness-balanced multilevel partitioning for uniform resource utilization
In this paper, we propose a new multi-objective multilevel K-way partitioning which is aware of resource utilization distribution, assuming the resource utilization for a partitio...
Yongseok Cheon, Martin D. F. Wong
FPGA
2008
ACM
136views FPGA» more  FPGA 2008»
13 years 9 months ago
A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs
Functional full-system simulators are powerful and versatile research tools for accelerating architectural exploration and advanced software development. Their main shortcoming is...
Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Bab...
22
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GLVLSI
2003
IEEE
175views VLSI» more  GLVLSI 2003»
14 years 24 days ago
A custom FPGA for the simulation of gene regulatory networks
We present a unique FPGA that uses a mix of digital and large-signal analog computation for the simulation of gene regulatory networks. The prototype IC consists of a 4x5 array of...
Ilias Tagkopoulos, Charles A. Zukowski, German Cav...