87 search results - page 7 / 18 » FPGA power reduction using configurable dual-Vdd |
TCAD
2008
13 years 7 months ago
2008
This paper explores, develops, and investigates several bypass-sensitive compilation techniques to reduce the register file power by reducing the access frequency to the register f...
DATE
2000
IEEE
13 years 12 months ago
2000
IEEE
Traditional FPGA design flows have treated logic synthesis and physical design as separate steps. With the recent advances in technology, the lack of information on the physical ...
ICCAD
2007
IEEE
14 years 4 months ago
2007
IEEE
—In this paper, we introduce a novel reconfigurable architecture, named 3D nFPGA, which utilizes 3D integration techniques and new nanoscale materials synergistically. The propos...
FPL
2003
Springer
14 years 20 days ago
2003
Springer
Distributed Arithmetic techniques are widely used to implement Sum-of-Products computations such as calculations found in multimedia applications like FIR filtering and Discrete Co...
FPL
2005
Springer
14 years 1 months ago
2005
Springer
This paper presents a configuration memory architecture that offers fast FPGA reconfiguration. The underlying principle behind the design is the use of fine-grained partial rec...