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IPPS
1996
IEEE
14 years 22 days ago
Implementation of a SliM Array Processor
This paper presents the design and implementation of a Sliding Memory Plane (SliM) Array Processor, a mesh-connected SIMD architecture. To build the array processor, we developed ...
Hyun M. Chang, Myung Hoon Sunwoo, Tai-Hoon Cho
IJCNN
2007
IEEE
14 years 2 months ago
Implementation of multi-layer leaky integrator networks on a cellular processor array
- We present an application of a massively parallel processor array VLSI circuit to the implementation of neural networks in complex architectural arrangements. The work was motiva...
David R. W. Barr, Piotr Dudek, Jonathan M. Chamber...
ISBI
2007
IEEE
14 years 2 months ago
Real-Time Mutual-Information-Based Linear Registration on the Cell Broadband Engine Processor
Emerging multi-core processors are able to accelerate medical imaging applications by exploiting the parallelism available in their algorithms. We have implemented a mutual-inform...
Moriyoshi Ohara, Hangu Yeo, Frank Savino, Giridhar...
ICPR
2004
IEEE
14 years 9 months ago
From Massively Parallel Image Processors to Fault-Tolerant Nanocomputers
Parallel processors such as SIMD computers have been successfully used in various areas of high performance image and data processing. Due to their characteristics of highly regula...
Jie Han, Pieter Jonker
ICPADS
2007
IEEE
14 years 2 months ago
Optimizing Katsevich image reconstruction algorithm on multicore processors
The Katsevich image reconstruction algorithm is the first theoretically exact cone beam image reconstruction algorithm for a helical scanning path in computed tomography (CT). Ho...
Eric Fontaine, Hsien-Hsin S. Lee