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CAGD
2005
88views more  CAGD 2005»
13 years 9 months ago
An efficient bit allocation for compressing normal meshes with an error-driven quantization
We propose a new wavelet compression algorithm based on the rate-distortion optimization for densely sampled triangular meshes. Exploiting the normal remesher of Guskov et al., th...
Frédéric Payan, Marc Antonini
AICOM
2004
100views more  AICOM 2004»
13 years 9 months ago
Query rewriting with symmetric constraints
Abstract. We address the problem of answering queries using expressive symmetric inter-schema constraints which allow to establish mappings between several heterogeneous informatio...
Christoph Koch
ISPASS
2009
IEEE
14 years 4 months ago
GARNET: A detailed on-chip network model inside a full-system simulator
Until very recently, microprocessor designs were computation-centric. On-chip communication was frequently ignored. This was because of fast, single-cycle on-chip communication. T...
Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, Nira...
DATE
1999
IEEE
120views Hardware» more  DATE 1999»
14 years 2 months ago
Hardware Synthesis from C/C++ Models
Software programming languages, such as C/C++, have been used as means for specifying hardware for quite a while. Different design methodologies have exploited the advantages of f...
Giovanni De Micheli
ICCAD
2002
IEEE
227views Hardware» more  ICCAD 2002»
14 years 6 months ago
Generic ILP versus specialized 0-1 ILP: an update
Optimized solvers for the Boolean Satisfiability (SAT) problem have many applications in areas such as hardware and software verification, FPGA routing, planning, etc. Further use...
Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Kare...